Barrier enhancement process for copper interconnects

ABSTRACT

A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10μ to 100μ and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority from U.S. ProvisionalApplication Serial No. 60/298,138, filed Jul. 25, 2001.

[0002] This invention relates to an electrochemical deposition processfor depositing a thin film enhancement layer onto an existing ultra thinbarrier layer to repair defects and enhance the barrier properties ofthe barrier layer. The deposited thin film enhancement layer serves as abarrier layer and as a seed layer for subsequent copper platingprocesses.

BACKGROUND OF THE INVENTION

[0003] Metallization patterns are needed to interconnect numerousdevices to form integrated circuits. For high performance ultra largescale integration (ULSI) chips, six or more metallization layers arecommonly used. The number of layers is expected to increase as theindustry works to decrease device dimensions and pack more devices ontointegrated circuit chips.

[0004] Integrated circuit chip performance is limited by the signalpropagation delay of the interconnections, also known as the “RC” delay.In order to improve circuit speed, it is important to reduce both the R(the resistance) and the C (the capacitance) associated with theinterconnections. Recently, copper metallization has been introduced toreplace aluminum metallization in integrated circuit fabrication becausecopper has both a lower resistivity and a higher current carryingcapacity than aluminum.

[0005] Copper metallization requires different processing than aluminummetallization. Instead of metal deposition followed by patterning asused in forming aluminum interconnects, copper interconnects usually areformed using a damascene process. In a damascene process, the conductorpattern is first etched into the dielectric material. Then, the etchedpatterns are filled with copper. Excess copper then is removed from overthe field using a chemical mechanical polishing (“CMP”) step. A via-holeis used to connect different metallization layers formed in theintegrated circuit chip. When the conductor line pattern and via-holepattern are filled and polished separately, the process is generallyreferred to as a “single damascene” process. When both the conductorline and the via-hole pattern are filled at the same time, the processis generally referred to as a “dual damascene” process.

[0006] In the known damascene process, a barrier layer and then a seedlayer are deposited over the patterned dielectric layer surface beforecopper is introduced. The barrier layer is needed to prevent the copperfrom diffusing into the device region. When in contact with silicon,copper spoils the silicon device operation. Usually, thin refractorymetals or metal nitrides are selected for the barrier layer.Representative barrier layer materials include tantalum, tantalumnitride, tungsten, tungsten nitride, titanium and titanium nitride. Theseed layer is needed to provide the conductivity for the electrochemicaldeposition reaction and to provide nucleation sites for the subsequentcopper electroplating. Usually, a thin copper layer is deposited overthe barrier layer to serve as the seed layer.

[0007] One of the most important requirements for the damascene processfor copper is to have the deposited copper perfectly fill the smallgeometries of etched lines or trenches and holes with high aspect ratios(calculated as depth divided by width). Electroplating processes aregenerally used to deposit copper because such processes have better gapfilling capability as compared to physical vapor deposition (“PVD”) orchemical vapor deposition (“CVD”). Because electrochemical copperdeposition processes can deposit more copper inside small trenches thanoutside the trenches, they are frequently called “super-filling.”

[0008] The PVD techniques include, for example, various evaporation andsputtering techniques, such as DC and/or RF plasma sputtering, biassputtering, magnetron sputtering, ion plating, or ionized metal plasmasputtering. PVD processes generally produce non-conformal deposition dueto their anisotropic and directional nature. The CVD techniques include,for example, thermal CVD, plasma enhanced CVD, low pressure CVD, highpressure CVD, and metal-organo CVD. CVD processes most frequentlyproduce conformal deposition with substantially uniform thickness overthe entire surface, including over the field and the bottom and sidewallsurfaces of the openings.

[0009] Currently, the barrier and seed layers are deposited primarily byPVD processes, such as sputtering and ionized sputtering. Frequently,the barrier and seed layers are deposited sequentially in two differentvacuum chambers without breaking vacuum to avoid surface contamination.The critical factor in such deposition processes is the film thicknessinside the etched patterns, particularly on the sidewall and bottom ofetched lines or trenches and via holes. The PVD processes commonly formthinner film layers in these etched patterns than over the flat fieldregion of the dielectric material. The step coverage of these layers hasbeen problematic. The films must be continuous and defect free. A voidor defect in the barrier layer will compromise the integrity of thedevice. A void or defect in the seed layer will lead to a void or defectin the plated copper film.

[0010] To improve step coverage, CVD processes have been tried fordepositing the barrier and seed layers. The CVD processes have notyielded better results than the PVD processes, and CVD processes aremore expensive. Copper seed layers deposited by CVD processes usuallyhave poor adhesion, higher impurities and poor crystal orientation,leading to problems when additional copper is electrochemicallydeposited over such seed layers. Sometimes PVD is used in conjunctionwith CVD, such that a separate copper seed layer is deposited by PVDprocessing over a copper seed layer deposited by CVD, further adding tothe expense for CVD processing. Accordingly, PVD processing for barrierand seed layers for copper interconnects has remained preferred despitenoted difficulties with step coverage.

[0011] Improvements to PVD deposition technology may not suffice tosolve problems with film coverage for the barrier layers and seed layersdeposited by PVD. As device dimensions continue to decrease, in thefuture the barrier film layer on the trench sidewall will need to beless than 10 nanometers. Combined technologies may be required to meetthe more rigorous requirements.

[0012] U.S. Pat. No. 6,136,707 teaches a method of combining a firstcopper seed layer formed by CVD with a second copper seed layer formedby PVD. U.S. Pat. No. 6,197,181 discloses a method of combining a firstcopper seed layer electrolytically deposited from an alkaline platingsolution with a second copper seed layer formed by PVD. Both of thesepatents thus require additional processing steps to achieve better PVDcopper seed layer adhesion. However, the methods disclosed in thesepatents do not solve the problems caused by either a defective barrierlayer or a poor interface between the barrier layer and the copper seedlayer.

[0013] Accordingly, the industry seeks better methods forelectrochemically depositing copper into high aspect ratio holes andtrenches.

SUMMARY OF THE INVENTION

[0014] The invention comprises processes and apparatus for applying ametal to a microelectronic workpiece where the microelectronic workpieceincludes a surface in which are disposed one or more micro-recessedstructures. Most commonly, the microelectronic workpiece is asemiconductor wafer, such as a silicon or gallium arsenide semiconductorwafer. Preferably, the metal is copper applied to form metallizationlayers in trenches or holes or vias or other structures in thesemiconductor wafer using a damascene or dual damascene process.

[0015] In the process according to the invention, the steps comprise:

[0016] (a) forming a barrier layer on the surface of the microelectronicworkpiece, including on the walls of the micro-recessed structures;

[0017] (b) forming an enhancement layer over the barrier layer, whereinsaid enhancement layer is comprised of a metal alloy; and

[0018] (c) electroplating a metal onto the enhancement layer so as tofill the micro-recessed structure.

[0019] Preferably, the enhancement layer is formed to a thickness of100μ or less, most preferably from 10μ to 100μ, using an electrochemicaldeposition process, such as an electroless or an electroplating process.Alternatively, the enhancement layer may be formed using a CVD or PVDprocess.

[0020] In one embodiment, the enhancement layer is formed from a copperalloy, such as Cu—Al, Cu—Mg and/or Cu—Zn. In another embodiment, theenhancement layer is formed from a binary alloy composition, such asCo—P, or a tertiary alloy composition, such as Co—W—P.

[0021] The enhancement layer conformally covers the barrier layer, evenwhere the barrier layer has seams, discontinuities or grain boundarydefects. For a silicon semiconductor wafer, the barrier layer may betitanium, titanium nitride, or other known barrier layer materials. Theenhancement layer is conductive sufficient to permit deposition of ametal, preferably copper, thereon. Thereafter, excess metal is removedfrom the field surface, such as by chemical mechanical polishing. Thedeposited metal remains within the microelectronic structure forming thedesired interconnect or metallization layer.

[0022] In a further embodiment, the process steps comprise:

[0023] (a) forming a barrier layer on the surface of the microelectronicworkpiece, including on the walls of the micro-recessed structures;

[0024] (b) forming an enhancement layer of a metal alloy over thebarrier layer;

[0025] (c) forming a seed layer over the enhancement layer; and

[0026] (d) electroplating a metal onto the enhancement layer so as tofill the micro-recessed structure.

[0027] In this alternate embodiment, the seed layer may comprise afurther layer of a metal alloy or may comprise a layer of the metalintended to be deposited in the microelectronic structure. Thus, theseed layer may be a copper alloy, a binary alloy such as Co—P, or atertiary alloy such as Co—W—P. The seed layer is formed with a thicknesspreferably from 50μ to 500μ.

[0028] The damascene processes may be carried out in a manufacturingline including a plurality of apparatus for the manufacture ofmicroelectronic circuits or components, where one or more apparatus ofthe plurality of apparatus are used to apply interconnect metallizationin a damascene process to a surface of a microelectronic workpiece usedto form the microelectronic circuits or components. The microelectronicworkpiece preferably is a silicon or gallium arsenide semiconductorwafer into which has been formed holes or trenches or vias suited formetallization to form microelectronic circuits or components. In suchcase, the one or more apparatus comprise:

[0029] means for applying a barrier layer to a surface of themicroelectronic workpiece using a first deposition process, wherein thebarrier layer is generally unsuitable for bulk electrochemicaldeposition of the interconnect metallization;

[0030] means for applying an enhancement layer over the barrier layerusing a second deposition process, wherein the enhancement layer formedfrom an alloy composition that is generally suitable for subsequentelectrochemical application of a metal to a predetermined thicknessrepresenting a bulk portion of the interconnect metallization; and

[0031] means for electrochemical application of a metal over theenhancement layer.

[0032] Preferably, the means for applying the enhancement layer isequipment for electrochemical deposition, such as equipment forelectroless or electroplating processing. Alternatively, the means forapplying the enhancement layer may be equipment for CVD or PVDprocessing. The means for applying the enhancement layer is capable ofapplying the enhancement layer conformally over the barrier layer to athickness of 100μ or less, preferably from 10μ to 100μ thick. Theenhancement layer preferably is formed from a metal alloy, such as acopper alloy like Cu—Al, Cu—Mg and/or Cu—Zn, a binary alloy such asCo—P, or a tertiary alloy such as Co—W—P, or possibly even from mixturesof such alloys.

[0033] The means for electrochemical application of a metal over theenhancement layer is capable of applying copper as the metal in thedamascene process. Once the copper is introduced into the metallizationlayers or microelectronic structures, a means is provided for removing aportion of the copper metal from the field surface of themicroelectronic workpiece. Preferably, the means for removing a portionof the copper metal comprises chemical mechanical polishing equipment.

[0034] The apparatus may include a first chamber for applying thebarrier layer and a second chamber for applying the enhancement layer.In addition, the optional additional seed layer and the coppermetallization layer may be deposited onto the workpiece while theworkpiece is in the second chamber used to apply the enhancement layer.Thus, electrochemical deposition of the enhancement layer, the optionalseed layer, and the copper metal may be carried out in a single chamberin the apparatus.

DESCRIPTION OF THE FIGURES

[0035] The invention will be more fully understood by referring to thedetailed specification and claims taken in connection with the followingdrawings.

[0036]FIG. 1A is a cross-sectional view illustrating a siliconsemiconductor wafer that has been etched to form a dielectric patterntrench;

[0037]FIG. 1B is a cross-sectional view illustrating the siliconsemiconductor wafer with a trench wherein a thin barrier layer, such astantalum or tantalum nitride, is shown as deposited uniformly over thesurface;

[0038]FIG. 2 is a cross-sectional view of a silicon semiconductor waferwith a trench that has been coated with a thin barrier layer, andillustrating surface defects most commonly formed in the thin barrierlayer;

[0039]FIG. 2A is an enlarged cross-sectional view of the coated siliconsemiconductor wafer trench of FIG. 2;

[0040]FIG. 3 is a cross-sectional view of the silicon semiconductorwafer with a trench that has been coated first with a thin barrierlayer, and then with a barrier enhancement layer according to theinvention;

[0041]FIG. 4 is a cross-sectional view of the silicon semiconductorwafer of FIG. 3, wherein the trench has been filled with copper using anelectrochemical deposition method;

[0042]FIG. 5 is a cross-sectional view of the silicon semiconductorwafer of FIG. 4 after the surface has been polished to remove excesscopper, leaving a completed damascened conductor pattern;

[0043]FIG. 6 is a cross-sectional view of an alternate embodimentwherein the silicon semiconductor wafer has a completed damascenedconductor pattern, and wherein a copper seed layer has been depositedover the barrier enhancement layer before the trench was filled withcopper; and

[0044]FIG. 7 is a graph of the deposition rate of Co—W—P alloy barrierenhancement film over a barrier layer at 75° C. in angstroms versus timein minutes.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] Referring first to FIG. 1A, a silicon dielectric material 10,such as SiO₂, comprises a semiconductor wafer shown in enlarged partialcross-sectional view. The dielectric material 10 has a trench 12 formedtherein.

[0046] The surface of the dielectric material 10 is coated with a thinbarrier layer 14, preferably using a PVD process although a CVD processmay also be used. The barrier layer generally may be a thin refractorymetal or metal nitride. Representative barrier layer materials includetantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungstennitride, tungsten silicon nitride, titanium, titanium nitride andtitanium silicon nitride, and other tertiary nitrides.

[0047] As shown in FIG. 1A, the barrier layer 14 is formed as acontinuous layer or film without discontinuities or surface defects.This is the ideal surface coverage for such a barrier layer. The barrierlayer thickness is generally from 100μ to 500μ over the field and flatbottom surfaces within the trench, and depending upon the aspect ratioand opening size of the trench, 100μ or less over the trench sidewall.For very small openings with large depths, the deposited film on thesidewall can be too thin, resulting in discontinuities and surfacedefects.

[0048] Referring next to FIGS. 2 and 2A, the barrier layer 16 formedover the dielectric material 10 is shown to have surface coveragedefects within the trench 12. As illustrated in FIG. 2, the barrierlayer 16 has not smoothly covered the trench sidewall and flat bottomsurface. Seams 18 are left in the bottom corners where the barrier layerhas not covered the dielectric material. Discontinuities 20 are breaksin the coverage along the sidewalls. Grain boundaries 22 representsurface defects that inhibit proper adhesion of a subsequent copper seedlayer to be formed over the barrier layer in the known damasceneprocess.

[0049] Most of the failures in the barrier layer relate to copperdiffusion at the grain boundaries because grain boundary diffusion ismuch faster than the diffusion through the bulk. It has been proposed to“stuff” the grain boundaries to improve the barrier properties of thebarrier layer with grain boundary defects. For example, TiN barrierlayers are usually annealed in an oxygen atmosphere to “stuff” theoxygen at the grain boundaries. Another method to reduce the diffusionat the grain boundaries is to add other materials to the originalbarrier metal to form alloys. The added material usually concentrates atthe grain boundaries (also called segregation). Alloy composition can beadjusted to satisfy different requirements. For example, copper alloys,such as Cu—Sn, Cu—Zn, Cu—Mg or Cu—Al can be used as diffusion barriersfor copper. The added metal in the alloy usually concentrates on thegrain boundary surface or free surface and prevents the copper atomsfrom moving. Cu—Sn and Cu—Zn are known to slow the corrosion of Cu inair by preventing oxygen diffusion. Recently, Cu—Al has been studied asa diffusion barrier for copper because Al tends to segregate out at thegrain boundaries and at the surface.

[0050] One of the most difficult issues in depositing a seed layer overthe barrier layer is getting good adhesion between the original barrierlayer and the seed layer deposited thereon. Plated copper adheres poorlyto the barrier layer surface. That is why the seed enhancement layerdescribed in U.S. Pat. No. 6,197,181 was not directly deposited on thebarrier layer, but was deposited onto a PVD deposited copper seed layer.A CVD copper seed layer directly deposited onto the barrier layer alsohas poor adhesion, and a PVD copper seed layer is often used to improvethe adhesion of the CVD copper seed layer.

[0051] According to the invention, as shown in FIG. 3, a barrierenhancement layer 24 is deposited conformally over the barrier layer 16,using either a CVD process, a PVD process or an electrochemical process.An electrochemical process or a CVD process are preferred. Anelectrochemical deposition process, such as electroless andelectroplating processes, are most preferred. The barrier enhancementlayer is from 10μ to 100μ thick, and covers the defects, such as theseams 18, the discontinuities 20, and the grain boundaries 22 present inthe barrier layer 16. The barrier enhancement layer has good stepcoverage.

[0052] The barrier enhancement layer 24 is intended both to enhance theperformance of the diffusion barrier layer and to serve as a seed layerfor subsequent copper plating processing. Thus, depositing the barrierenhancement layer can eliminate the need for a separate copper seedlayer.

[0053] The barrier enhancement layer is formed from a conductive metalthat will adhere to the barrier layer and will also permit subsequentcopper plating. Preferably, the barrier enhancement layer is formed froma binary or tertiary metal alloy material selected from one of thefollowing: cobalt-phosphorous (Co—P) or cobalt-tungsten-phosphorous(Co—W—P); or is formed from a copper alloy, such as Cu—Al, Cu—Mg, Cu—Znand/or Cu—Sn, or possibly mixtures of such alloys.

[0054] Preferably, the alloy material deposited as the barrierenhancement layer is Co—W—P. Electrochemical deposition processes forCo—W—P are described in detail in U.S. Pat. No. 5,695,810, whichdescription is incorporated herein by reference. Typical depositiontemperatures for this alloy range from room temperature to 90° C.However, at 90° C., the loss of aqueous electrolyte by evaporation maybe excessive, such that a lower temperature, such as 75° C. ispreferred. The thickness of the deposited Co—W—P layer can be controlledby controlling the deposition time and temperature for a givendeposition chemistry. Co—W—P alloy material deposits over a TiN barrierlayer at a rate of about 100μ to 200μ per minute at 75° C. in anelectrochemical deposition process as graphically illustrated in FIG. 6.

[0055] The electrochemical deposition processes are preferred fordepositing the barrier enhancement layer. Such processes are compatiblewith the standard copper plating process and equipment already in use incopper interconnect fabrication. The new electrochemical depositionprocess for the barrier enhancement layer therefore can readily beintegrated with existing plating tools by installing a new processchamber in the existing system. A suitable integrated tool configurationis shown in FIG. 12 in U.S. Pat. No. 6,017,437. The integrated toolconfiguration reduces tooling costs and permits a simple waferprocessing flow sequence. After the barrier enhancement layer isdeposited, the wafer can be transferred directly to the copper platingmodule to complete the plating process without leaving the plating tool.

[0056] After the barrier enhancement layer 24 is applied over thebarrier layer 16, the etched pattern is filled with electroplated copperas shown in FIG. 4. Thereafter, the field surface is polished,preferably by a chemical mechanical polishing (“CMP”) step, to removethe excess copper. A completed damascened conductor pattern after theCMP is completed is shown in FIG. 5.

[0057] In an alternate embodiment, two separate layers may be depositedonto the barrier layer. As shown in FIG. 6, the enlarged cross-sectionalview of the dielectric wafer material 10 has a trench 12 formed therein.A barrier layer 16 is deposited over flat bottom and sidewall surfacesof the trench, and has grain boundaries, seams and discontinuitiestherein as noted in the prior embodiment. The barrier enhancement layer24 is again applied over the barrier layer 16. Thereafter, a seed layer28 is formed over the barrier enhancement layer 24. The seed layer 28may be formed as an alloy, such as used to form the barrier enhancementlayer 24 or may be copper metal. Although the seed layer may bedeposited by a CVD, PVD or electrochemical deposition process, theelectrochemical deposition processes are preferred. Moreover, it is moreeconomical to deposit the barrier enhancement layer and the seed layerusing compatible deposition processes, and preferably in the same tool.

EXAMPLES Example 1

[0058] A single barrier enhancement layer was deposited over a TiNbarrier layer. The TiN barrier layer was sputtered over a silicondioxide dielectric material. The TiN barrier layer surface was thencleaned and rinsed. A thin electroless Co—W—P layer was then depositedover the TiN barrier layer. The electrolyte used for depositionconsisted of: CoCl × 6 H₂O 30 g/l (NH₄)₂WO₄ 10 g/l Na₃C₆H₅O₇ × H₂O 80g/l NaH₂PO₂ × H₂O 20 g/l KOH to pH = 9.5

[0059] The deposition temperature was 75° C. and deposition time wasabout one minute. The deposited film (about 100μ) had good diffusionproperties and was used successfully as the seed layer for subsequentcopper plating.

Example 2

[0060] A sputtered tantalum barrier layer was applied to the silicondioxide dielectric substrate. Because direct deposition of Co—W—P ontotantalum is known to have marginal adhesion, a thin layer (about 100μ)of cobalt was sputtered onto the tantalum surface. Then, a layer ofCo—W—P was deposited by electroless deposition onto the sputtered Cosurface at 75° C. for about one minute. The combined film (approximately200μ) resulted in satisfactory adhesion. Copper was then directlyelectroplated onto the Co—W—P layer. In this example, the Co layer wasthe barrier enhancement layer and the Co—W—P was the seed layer forcopper plating.

[0061] This example illustrates that according to the second embodimentof the invention: (1) two different layers may be used—a barrierenhancement layer and a seed layer; and (2) different depositiontechniques were used for depositing the barrier enhancement layer andthe seed layer.

[0062] The invention has been illustrated by detailed description andexamples of the preferred embodiments. Various changes in form anddetail will be within the skill of persons skilled in the art.Therefore, the invention must be measured by the claims and not by thedescription of the examples or the preferred embodiments.

We claim:
 1. A process for applying a metal to a microelectronicworkpiece, the microelectronic workpiece including a surface in whichare disposed one or more micro-recessed structures, the processcomprising: (d) forming a barrier layer on the surface of themicroelectronic workpiece, including on the walls of the micro-recessedstructures; (e) forming an enhancement layer over the barrier layer,wherein said enhancement layer is comprised of a metal alloy; and (f)electroplating a metal onto the enhancement layer so as to fill themicro-recessed structure.
 2. The process of claim 1, wherein theenhancement layer is formed using an electrochemical deposition process.3. The process of claim 2, wherein the electrochemical depositionprocess is selected from the group consisting of electroless andelectroplating processes.
 4. The process of claim 1, wherein theenhancement layer is formed using a CVD process.
 5. The process of claim1, wherein the enhancement layer is formed using a PVD process.
 6. Theprocess of claim 1, wherein the enhancement layer is formed with athickness of 100μ or less.
 7. The process of claim 1, wherein theenhancement layer is formed with a thickness in the range of from 10μ to100μ thick.
 8. The process of claim 1, wherein the barrier layer soformed has seams, discontinuities or grain boundary defects, and whereinthe enhancement layer conformally covers the barrier layer.
 9. Theprocess of claim 1, wherein the enhancement layer is formed from acopper alloy.
 10. The process of claim 9, wherein the copper alloy isselected from the group consisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, andmixtures of such alloys.
 11. The process of claim 1, wherein theenhancement layer is formed from a binary alloy composition.
 12. Theprocess of claim 11, wherein the alloy is Co—P.
 13. The process of claim1, wherein the enhancement layer is formed from a tertiary alloycomposition.
 14. The process of claim 13, wherein the alloy is Co—W—P.15. The process of claim 1, wherein the metal electroplated onto theenhancement layer is copper.
 16. The process of claim 1, furthercomprising: (d) removing a portion of the metal from the surface of themicroelectronic workpiece.
 17. The process of claim 16, wherein theremoving is by chemical mechanical polishing.
 18. The process of claim1, wherein the microelectronic workpiece is a silicon or galliumarsenide semiconductor wafer.
 19. A metallization layer formed in amicroelectronic workpiece according to the process of claim
 1. 20. Aprocess for applying a metal to a microelectronic workpiece, themicroelectronic workpiece including a surface in which are disposed oneor more micro-recessed structures, the process comprising: (a) forming abarrier layer on the surface of the microelectronic workpiece, includingon the walls of the micro-recessed structures; (b) forming anenhancement layer of a metal alloy over the barrier layer; (c) forming aseed layer over the enhancement layer; and (d) electroplating a metalonto the enhancement layer so as to fill the micro-recessed structure.21. The process of claim 20, wherein the enhancement layer is formedusing an electrochemical deposition process.
 22. The process of claim21, wherein the electrochemical deposition process is selected from thegroup consisting of electroless and electroplating processes.
 23. Theprocess of claim 20, wherein the enhancement layer is formed using a CVDprocess.
 24. The process of claim 20, wherein the enhancement layer isformed using a PVD process.
 25. The process of claim 20, wherein theenhancement layer is formed with a thickness of 100μ or less.
 26. Theprocess of claim 20, wherein the enhancement layer is formed with athickness in the range of from 10μ to 100μ thick.
 27. The process ofclaim 20, wherein the barrier layer so formed has seams, discontinuitiesor grain boundary defects, and wherein the enhancement layer conformallycovers the barrier layer.
 28. The process of claim 20, wherein theenhancement layer is formed from a copper alloy.
 29. The process ofclaim 28, wherein the copper alloy is selected from the group consistingof: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, and mixtures of such alloys.
 30. Theprocess of claim 20, wherein the enhancement layer is formed from abinary alloy composition.
 31. The process of claim 30, wherein the alloyis Co—P.
 32. The process of claim 20, wherein the enhancement layer isformed from a tertiary alloy composition.
 33. The process of claim 32,wherein the alloy is Co—W—P.
 34. The process of claim 20, wherein themetal electroplated onto the enhancement layer is copper.
 35. Theprocess of claim 20, further comprising: (e) removing a portion of themetal from the surface of the microelectronic workpiece.
 36. The processof claim 35, wherein the removing is by chemical mechanical polishing.37. The process of claim 20, wherein the microelectronic workpiece is asilicon or gallium arsenide semiconductor wafer.
 38. A metallizationlayer formed in a microelectronic workpiece according to the process ofclaim
 20. 39. In a manufacturing line including a plurality of apparatusfor the manufacture of microelectronic circuits or components, one ormore apparatus of the plurality of apparatus being used for applyinginterconnect metallization in a damascene process to a surface of amicroelectronic workpiece used to form the microelectronic circuits orcomponents, the one or more apparatus comprising: means for applying abarrier layer to a surface of the microelectronic workpiece using afirst deposition process, wherein the barrier layer is generallyunsuitable for bulk electrochemical deposition of the interconnectmetallization; means for applying an enhancement layer over the barrierlayer using a second deposition process, wherein the enhancement layerformed from an alloy composition that is generally suitable forsubsequent electrochemical application of a metal to a predeterminedthickness representing a bulk portion of the interconnect metallization;and means for electrochemical application of a metal over theenhancement layer.
 40. The manufacturing line of claim 39, wherein themeans for applying the enhancement layer is equipment forelectrochemical deposition.
 41. The manufacturing line of claim 40,wherein the means for applying the enchancement layer performs anelectrochemical deposition process selected from the group consisting ofelectroless and electroplating processes.
 42. The manufacturing line ofclaim 39, wherein the means for applying the enhancement layer isequipment for CVD processing.
 43. The manufacturing line of claim 39,wherein the means for applying the enhancement layer is equipment forPVD processing.
 44. The manufacturing line of claim 39, wherein themeans for applying the enhancement layer is capable of applying theenhancement layer conformally over the barrier layer to a thickness of100μ or less.
 45. The manufacturing line of claim 39, wherein theenhancement layer is formed from a metal alloy selected from the groupconsisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P, and Co—W—P, andmixtures thereof.
 46. The manufacturing line of claim 39, the means forelectrochemical application of a metal over the enhancement layer iscapable of applying copper as the metal.
 47. The manufacturing line ofclaim 39, further comprising: means for removing a portion of the metalfrom the surface of the microelectronic workpiece.
 48. The manufacturingline of claim 47, wherein the means for removing a portion of the metalcomprises chemical mechanical polishing equipment.
 49. The manufacturingline of claim 39, wherein the microelectronic workpiece is a silicon orgallium arsenide semiconductor wafer.
 50. An apparatus for applyinginterconnect metallization in a damascene process to a surface of amicroelectronic workpiece used to form microelectronic circuits orcomponents, comprising: means for applying a barrier layer to a surfaceof the microelectronic workpiece using a first deposition process,wherein the barrier layer is generally unsuitable for bulkelectrochemical deposition of the interconnect metallization; means forapplying an enhancement layer over the barrier layer using a seconddeposition process, wherein the enhancement layer formed from an alloycomposition that is generally suitable for subsequent electrochemicalapplication of a metal to a predetermined thickness representing a bulkportion of the interconnect metallization; and means for electrochemicalapplication of a metal over the enhancement layer.
 51. The apparatus ofclaim 50, wherein the means for applying the enhancement layer isequipment for electrochemical deposition.
 52. The apparatus of claim 51,wherein the means for applying the enchancement layer performs anelectrochemical deposition process selected from the group consisting ofelectroless and electroplating processes.
 53. The apparatus of claim 51,wherein the electrochemical deposition equipment comprises a chamber,one or more electrodes, one or more cathodes and a processing fluid tocouple the one or more electrodes and the one or more cathodes to themicroelectronic workpiece.
 54. The apparatus of claim 53, wherein theprocessing fluid is an electrolyte for electroplating copper or a metalalloy selected from the group consisting of: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn,Co—P, and Co—W—P, and mixtures.
 55. The apparatus of claim 50, whereinthe means for applying the enhancement layer is capable of applying theenhancement layer conformally over the barrier layer to a thickness of100μ or less.
 56. The apparatus of claim 50, wherein the enhancementlayer is formed from a metal alloy selected from the group consistingof: Cu—Al, Cu—Mg, Cu—Zn, Cu—Sn, Co—P, and Co—W—P.
 57. The apparatus ofclaim 50, the means for electrochemical application of a metal over theenhancement layer is capable of applying copper as the metal.
 58. Theapparatus of claim 50, wherein the means for applying the barrier layeris within a first chamber and the means for applying the enhancementlayer is within a second chamber of the apparatus.
 59. The apparatus ofclaim 50, wherein the means for applying the enhancement layer is withina first chamber and the means for applying the metal over theenhancement layer is within a second chamber of the apparatus.
 60. Theapparatus of claim 50, wherein the means for applying the enhancementlayer is within a first chamber and the means for applying a metal overthe enhancement layer comprises the same means within the first chamberof the apparatus.
 61. The apparatus of claim 50, wherein themicroelectronic workpiece is a silicon or gallium arsenide semiconductorwafer.